Digital System Test And Testable Design: Using ... Direct

Gate-level faults, fault collapsing, and structural modeling in Verilog.

Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs. Digital System Test and Testable Design: Using ...

Random and deterministic test generation methods, plus sequential circuit test generation. Digital System Test and Testable Design: Using ...

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies. Digital System Test and Testable Design: Using ...